By Ibrahim (Abe) M. Elfadel, Gerhard Fettweis
This booklet explains for readers how 3D chip stacks promise to extend the extent of on-chip integration, and to layout new heterogeneous semiconductor units that mix chips of alternative integration applied sciences (incl. sensors) in one package deal of the smallest attainable measurement. The authors specialise in heterogeneous 3D integration, addressing one of the most very important demanding situations during this rising know-how, together with contactless, optics-based, and carbon-nanotube-based 3D integration, in addition to signal-integrity and thermal administration concerns in copper-based 3D integration. insurance additionally contains the 3D heterogeneous integration of strength resources, photonic units, and non-volatile thoughts in line with new fabrics systems.
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Extra resources for 3D Stacked Chips: From Emerging Processes to Heterogeneous Systems
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An increased number of active elements will result in increased power consumption, which leads to more heat generation. By splitting one active layer of a 2D chip design into several stacked active layers of a 3D chip stack with only a fraction of the original footprint, the heat dissipation capability is reduced dramatically. Therefore, energy efficient design and power management become even more important compared to 2D SoC designs. A TSV is mainly a low ohmic interconnect having a capacitance against its surrounding substrate.