ARM Architecture Reference Manual (2nd Edition) by David Seal

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By David Seal

Produced through the architects which are actively engaged on the ARM specification, this ebook includes specific information regarding all types of the ARM and ThumbTM guide units, the reminiscence administration and cache services, and optimized code examples. either an architectural evaluate and programmer's version are provided. insurance additionally contains 26-bit architectures and the procedure keep watch over Coprocessor.

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Example text

It can often be used in place of one of the general-purpose registers R0 to R14, and is therefore considered one of the general-purpose registers. However, there are also many instruction-specific restrictions or special cases about its use. These are noted in the individual instruction descriptions. Usually, the instruction is UNPREDICTABLE if R15 is used in a manner that breaks these restrictions. The Program Counter is always used for a special purpose, as described in: • Reading the program counter • Writing the program counter on page A2-8.

To do this use: SUBS PC,R14,#4 ARM DDI 0100E Copyright © 1996-2000 ARM Limited. All rights reserved. 3 Software Interrupt exception The Software Interrupt instruction (SWI) enters Supervisor mode to request a particular supervisor (operating system) function. 4 Prefetch Abort (instruction fetch memory abort) A memory abort is signaled by the memory system. Activating an abort in response to an instruction fetch marks the fetched instruction as invalid. A Prefetch Abort exception is generated if the processor tries to execute the invalid instruction.

The condition code flags in the CPSR can be tested by most instructions to determine whether the instruction is to be executed. The condition code flags are usually modified by: • Execution of a comparison instruction (CMN, CMP, TEQ or TST). • Execution of some other arithmetic, logical or move instruction, where the destination register of the instruction is not R15. Most of these instructions have both a flag-preserving and a flag-setting variant, with the latter being selected by adding an S qualifier to the instruction mnemonic.

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