Cache and Memory Hierarchy Design. A Performance Directed by Steven A. Przybylski

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By Steven A. Przybylski

An authoritative booklet for and software program designers. Caches are through some distance the easiest and most suitable mechanism for bettering machine functionality. This leading edge e-book exposes the features of performance-optimal unmarried and multi-level cache hierarchies via coming near near the cache layout strategy in the course of the novel viewpoint of minimizing execution occasions. It offers worthy information at the relative functionality of a large spectrum of machines and gives empirical and analytical reviews of the underlying phenomena. This ebook may also help laptop pros savor the influence of caches and permit designers to maximise functionality given specific implementation constraints.

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4. Since the cache size is the most significant of the organizational design parameters, we begin by examining the important tradeoff between the system cycle time and the cache size. 1. Speed - Size Tradeoffs 1 1 1i i i i o b i i i i o 1 1 ii i i i i 11n o Ratio b As noted in Chapter 2, the usual cache metrics are miss rates and transfer ratios. Figure 4-1 confirms the widely held belief that larger caches are better in that the miss ratio declines with increasing cache size, but that beyond a certain size the incremental improvements are small [Agarwal 87b, Haikala 84b, Smith 85a].

Conversely, the delineated zones are the parts of the design space in which exchanging the RAMs for smaller yet faster ones is beneficial. In the unshaded area, such an exchange is warranted if the cycle time of the machine drops by only 5ns, again assuming a change in the cache size by a factor of four. With each region farther to the left, the cycle time improvement needed to justify the reduction in the cache size increases by 5ns. For example, consider a system being built around a 40ns CPU, requiring 15ns RAMs to attain that cycle time.

We can apply a few simplifying assumptions without a loss of generalization. For RISC machines with single-cycle execution, the number of cycles in which neither reference stream is active, NExecute , is zero. The CPU model used in the simulations exhibits this behaviour. As written, the above equation assumes that read references (instruction fetches and loads) take one cycle when they hit in the cache. It also assumes that there is a single port into a single cache, so that Cache and Memory Hierarchy Design 38 loads and instruction fetches are serialized.

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