Computer Architecture Techniques for Power-Efficiency by Stefanos Kaxiras

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By Stefanos Kaxiras

Within the previous few years, energy dissipation has develop into a huge layout constraint, on par with functionality, within the layout of latest desktops. while long ago, the first activity of the pc architect used to be to translate advancements in working frequency and transistor count number into functionality, now energy potency has to be taken under consideration at each step of the layout approach. whereas for your time, architects were winning in offering forty% to 50% annual development in processor functionality, bills that have been formerly pushed aside ultimately stuck up. the main severe of those bills is the inexorable raise in strength dissipation and tool density in processors. strength dissipation matters have catalyzed new subject components in desktop structure, leading to a considerable physique of labor on extra power-efficient architectures. energy dissipation coupled with diminishing functionality earnings, used to be additionally the most reason for the change from single-core to multi-core architectures and a slowdown in frequency elevate. This publication goals to record the most vital architectural thoughts that have been invented, proposed, and utilized to minimize either dynamic strength and static energy dissipation in processors and reminiscence hierarchies. an important variety of innovations were proposed for quite a lot of occasions and this ebook synthesizes these thoughts by way of concentrating on their universal features.

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An alternative method of cooling must be used. cls June 27, 2008 9:33 MODELING, SIMULATION, AND MEASUREMENT 21 alternative cooling is normally provided by pumping a liquid that is infrared transparent (such as mineral oil) over the microprocessor. In addition to providing dynamic cooling for the chip, the measurements also can benefit if the chip can be thinned in order to provide a more direct imaging path to the active silicon layer. That is, due to the bonding techniques typically used today, the active silicon layer lies face down in the socket, with the thicker silicon wafer material above it.

Cls 30 June 27, 2008 9:33 COMPUTER ARCHITECTURE TECHNIQUES FOR POWER-EFFICIENCY Profile-assisted compiler approach: Hsu and Kremer’s work provided a heuristic technique that lowers the voltage for memory-bound sections [103]. The intuition behind their approach is that if the processor and memory operate largely asynchronously from each other, then the processor can be dialed down to much lower clock frequencies during memory-bound regions, with considerable energy savings but no significant performance loss.

The repercussion of this choice is that no work is delayed past the end of the next interval. For large intervals, FUTURE approaches OPT in terms of energy savings, while for smaller ones it falls behind. Like OPT, FUTURE is also unrealistic for an on-line implementation, since it still peeks into the future. The PAST algorithm, which is the only one of the three suitable for an on-line implementation, looks into the past in order to predict the future. As with the previous algorithms, its interval size can be adjusted for different results.

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