By Francky Catthoor, K. Danckaert, K.K. Kulkarni, E. Brockmeyer, Per Gunnar Kjeldsberg, T. van Achteren, Thierry Omnes
Data entry and garage administration for Embedded Programmable Processors supplies an summary of the state of the art in system-level information entry and garage administration for embedded programmable processors. The detailed program area covers advanced embedded real-time multi-media and conversation functions. lots of those functions are data-dominated within the experience that their expense similar points, specifically strength intake and footprint are seriously stimulated (if now not ruled) by means of the information entry and garage points. the fabric is especially according to learn at IMEC during this zone within the interval 1996-2001. that allows you to care for the stringent timing specifications and the information ruled features of this area, we've got followed a objective structure sort that's suitable with sleek embedded processors, and we've got constructed a scientific step-wise method to make the exploration and optimization of such purposes possible in a source-to-source precompilation technique.
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Extra info for Data Access and Storage Management for Embedded Programmable Processors
Recently, further experiments have been performed to allow even more reduced storage requirements and to identify extensions for predefined memory organisations as in programmable DSP's [141, 143, 142, 149]. This has lead to a solid theoretical foundation for the in-place mapping task and the development of promising heuristics to solve this very complex problem in a reasonable CPU time in a 2-stage approach for M-D array signals [144, 146, 148]. These techniques have been implemented in a prototype tool for evaluating in-place storage of MD arrays.
Eindhoven, loop transformations on periodic streams have been applied to reduce an abstract storage and transfer cost [527, 529, 530, 531]. At Penn State [260, 256, 240] work on power oriented loop transformations has started. , improving data locality by unimodular transfonnations is addressed in . 3 Data-flow transformations Also data-flow transfonnations can effect the storage and transfer cost to memories quite heavily. This has been recognized in compiler work [8, 367] but automated steering methods have not been addressed there.
G. ). Also the cache behaviour is sometimes incorporated  but no real optimisations directed to the memory utilisation itself is integrated. 30 DATA ACCESS AND STORAGE MANAGEMENT FOR PROCESSORS Preliminary work on memory allocation in a GNU compiler script for minimizing memory interface traffic during hardware/software partitioning is described in . In a systolic (parallel) processor context, several processor allocation schemes have been proposed. g. with a solution approach based on a combination of the LSGP and LPGS approaches (see earlier).