Design of Very Large Scale Integration Systems by Linda E. Brackenbury

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By Linda E. Brackenbury

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In this technique Clock is applied in the reverse direction with respect to data so that clock skew is automatically eliminated. The receiving Flop will clock in the transmitting (source) value before the transmitting register receives its clock edge. 46 shows a simple example of implementing the clock reversing approach. 7 Controlling Clock Skew D 47 D Q D Q U3 CLK U2 CLK U1 CLK Q CLK Fig. 47 Clock reversing in a circular structure D Q 1 CLK D Q 2 CLK D 3 CLK Q D Q 4 CLK Fig. 48 Alternate edge clocking As shown when sufficient delay is inserted, the receiving Flop will receive the active-clock edge before the source Flop.

7 Controlling Clock Skew 45 Trdq1 D D1 Q D Q Routing Delay Tcq1 CLK CLK CLK2 CLK Tck2 Routing Delay Fig. 44 General delay blocks in a simple circuit CLK DATA2 CLK2 T1 H A SK H B SK H C SK CASE A: NO PROBLEM SK < T1 - H CASE B: PROBLEM SK > T1 - H CASE C: PROBLEM SK > T1 - H Fig. 45 Illustration of short path problem The short-path problem will definitely emerge in this circuit if Tck2 ! Tcq1  Trdq1  THOLD2 where THOLD2 is the hold-time requirement of the sink flip-flop. The regions are illustrated in Fig.

25. 5 Clock Gating Methodology 31 Clock Gating Cell TEST_SE EN Latch GATED_CLK CLK Fig. 26 Standard clock gating cell Since the latch captures the state of the enable signal and holds it until the complete clock pulse has been generated, the enable signal need only be stable around the rising edge of the clock. Using this technique, only one input of the gate that turns the clock on and off changes at a time, ensuring that the circuit is free from any glitches or spikes on the output. Note: Use an AND gate to gate a clock that is active on the rising edge.

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